Paper Info
Title
Layout driven data communication optimization for high level synthesis
Abstract
High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the final circuit layout. In this paper, we present a physically aware design flow for mapping high level application specifications to a synthesizable register transfer level hardware description. We study the problem of optimizing the data communication of the variables in the application specification. Our algorithm uses floorplan information that guides the optimization. We develop a simple, yet effective, incremental floorplanner to handle the perturbations caused by the data communication optimization. We show that the proposed techniques can reduce the wirelength of the final design, while maintaining a legal floorplan with the same area as the initial floorplan.
Year
DOI
Venue
2006
10.1109/DATE.2006.244021
DATE
Keywords
Field
DocType
high level application specification,legal floorplan,final circuit layout,application specification,synthesizable register transfer level,initial floorplan,layout driven data communication,final design,final circuit,floorplan information,high level synthesis transformation,design flow,register transfer level,hardware,law,integrated circuit layout,high level synthesis,registers,design optimization
Integrated circuit layout,Computer architecture,Computer science,Parallel computing,High-level synthesis,Design flow,Register-transfer level,Floorplan
Conference
Volume
ISSN
ISBN
1
1530-1591
3-9810801-0-6
Citations 
PageRank 
References 
2
0.39
10
Authors
7
Name
Order
Citations
PageRank
Ryan Kastner11779147.73
Wenrui Gong2856.82
Xin Hao3121.58
Forrest Brewer441462.95
Adam Kaplan526323.33
Philip Brisk678660.63
Majid Sarrafzadeh73103317.63