Name
Papers
Collaborators
FORREST BREWER
56
111
Citations 
PageRank 
Referers 
414
62.95
717
Referees 
References 
774
490
Search Limit
100774
Title
Citations
PageRank
Year
Distributed Pulse Rotary Traveling Wave VCO: Architecture and Design00.342019
Pulse Ring Oscillator Tuning via Pulse Dynamics10.362017
Design and analysis of high performance pulse ring VCO00.342017
High Performance Pulse Ring Voltage Controlled Oscillator For Internet Of Things00.342017
Low Complexity and Critical Path Based VLSI Architecture for LMS Adaptive Filter Using Distributed Arithmetic10.372017
Low phase noise pulse rotary wave voltage controlled oscillator00.342017
A Novel Co-design Methodology for Optimizing ESD Protection Device Using Layout Level Approach00.342016
Connectivity Effects on Energy and Area for Neuromorphic System with High Speed Asynchronous Pulse Mode Links.10.432016
Asynchronous High Speed Serial Links Analysis using Integrated Charge for Event Detection.10.392016
Formal verification of analog circuit parameters across variation utilizing SAT30.482013
Ongoing challenges in automated cyberphysical cross-domain design00.342013
A hierarchical Ant-Colony heuristic for architecture synthesis for on-chip communication00.342013
Automated MAC Protocol Generation with Multiple Neighborhoods and Acknowledgments Based on Symbolic Monte Carlo Simulation.20.422011
A Methodology for Optimal MAC Protocol Generation: Case Study of a Synchronous MAC Channel20.442010
Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID)90.992010
Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems00.342009
2009 MEMOCODE co-design contest50.622009
Control design for force balance sensors00.342009
Pulse-mode link for robust, high speed communications50.522008
Latency-Insensitive Hardware/Software Interfaces00.342008
Structural integrity: safety in miniature technology00.342008
Synthesizing synchronous elastic flow networks80.562008
MEMOCODE 2007 Co-Design Contest30.432008
Advances in ESL Design00.342008
Towards understanding architectural tradeoffs in MEMS closed-loop feedback control30.452007
Extensible control architectures10.362006
Layout driven data communication optimization for high level synthesis20.392006
A case study of multi-threading in the embedded space20.432006
Technical Program Committee00.342004
Buffer delay change in the presence of power and ground noise312.182003
Symbolic NFA scheduling of a RISC microprocessor00.342002
Coping with buffer delay change due to power and ground noise232.022002
Automata-based symbolic scheduling for looping DFGs90.612001
Representing and Scheduling Looping Behavior Symbolically20.382000
AQUILA: an equivalence checking system for large sequential designs211.042000
Power And Signal Integrity Improvement In Ultra High-Speed Current Mode Logic00.341999
A model for scheduling protocol-constrained components and environments20.421999
Efficient encoding for exact symbolic automata-based scheduling161.021998
Scheduling and binding bounds for RT-level symbolic execution40.541997
A new symbolic technique for control-dependent scheduling372.081996
Concurrent analysis techniques for data path timing optimization50.591996
Implementation of an efficient parallel BDD package442.081996
Clock skew optimization for ground bounce control365.171996
Symbolic scheduling techniques10.371995
Symbolic modeling and evaluation of data paths111.241995
Symbolic Scheduling Techniques.00.341995
Analysis of conditional resource sharing using a guard-based control representation130.791995
Incorporating speculative execution in exact control-dependent scheduling170.981994
Ensemble representation and techniques for exact control-dependent scheduling110.851994
Clairvoyant: a synthesis system for production-based specification327.661994
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