Paper Info
Title
Automatic generation of test sets for SBST of microprocessor IP cores
Abstract
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Currently, Software-Based Self-Test (SBST) is becoming an attractive test solution since it guarantees high fault coverage figures, runs at-speed, and matches core test requirements while exploiting low-cost ATEs. However, automatically generating test programs is still an open problem. This paper presents a novel approach for test program generation, that couples evolutionary techniques with hardware acceleration. The methodology was evaluated targeting a 5-stage pipelined processor implementing a SPARCv8 micro-processor core.
Year
DOI
Venue
2005
10.1145/1081081.1081105
SBCCI
Keywords
Field
DocType
core test requirement,sparcv8 microprocessor core,attractive test solution,automatic generation,5-stage pipelined processor,couples evolutionary technique,architectural evolution,test program,test program generation,software-based self-test,test set,microprocessor core,microprocessor ip core,software testing,assembly,design automation,fault coverage,verification,hardware accelerator,algorithms,performance,hardware,design,fpga
Open problem,Fault coverage,Computer science,Microprocessor,Field-programmable gate array,Real-time computing,Electronic design automation,Software,Hardware acceleration,Built-in self-test
Conference
ISBN
Citations 
PageRank 
1-59593-174-0
2
0.40
References 
Authors
16
4
Name
Order
Citations
PageRank
E. Sanchez113016.50
M. Sonza Reorda21099114.76
G. Squillero333030.36
Violante, M.420.40