Name
Affiliation
Papers
G. SQUILLERO
Politecnico di Torino
31
Collaborators
Citations 
PageRank 
36
330
30.36
Referers 
Referees 
References 
520
402
297
Search Limit
100520
Title
Citations
PageRank
Year
Increasing pattern recognition accuracy for chemical sensing by evolutionary based drift compensation50.632011
Automatic Generation of Software-based Functional Failing Test for Speed Debug and On-silicon Timing Verification30.442011
Design validation of multithreaded architectures using concurrent threads evolution20.392009
An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores160.782008
An evolutionary methodology for test generation for peripheral cores via dynamic FSM extraction40.562008
Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor20.382007
On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction00.342007
An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs200.942006
New evolutionary techniques for test-program generation for complex microprocessor cores30.472005
Evolving assembly programs: how games help microprocessor validation211.312005
On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors140.772005
Automatic generation of test sets for SBST of microprocessor IP cores20.402005
Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets10.402005
Code Generation for Functional Validation of Pipelined Microprocessors91.042004
Automatic test programs generation driven by internal performance counters90.782004
Coupling different methodologies to validate obsolete microprocessors00.342004
Fully Automatic Test Program Generation for Microprocessor Cores543.412003
An enhanced framework for microprocessor test-program generation71.252003
Automatic test program generation for pipelined processors91.032003
Initializability analysis of synchronous sequential circuits20.382002
Evolutionary test program induction for microprocessor design verification121.432002
An evolutionary algorithm for reducing integrated-circuit test application time10.372002
New Techniques for Speeding-Up Fault-Injection Campaigns372.462002
Evolving effective CA/CSTP: BIST architectures for sequential circuits30.432001
On the test of microprocessor IP cores474.352001
An RT-level fault model with high gate level correlation120.822000
Automatic test bench generation for validation of RT-level descriptions: an industrial experience262.362000
An improved cellular automata-based BIST architecture for sequential circuits10.362000
Exploiting the selfish gene algorithm for evolving cellular automata61.042000
Approximate equivalence verification of sequential circuits via genetic algorithms20.411999
A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits00.341997