Name
Title | ||
|---|---|---|
Dispatching of lots to dynamically reduce the wafers at risk in semiconductor manufacturing |
Abstract | ||
|---|---|---|
This paper presents a lot dispatching strategy to reduce the Wafer at Risk (W@R) on process tools, i.e. the number of wafers processed between two defectivity inspections. Due to the highly complex manufacturing process and the molecular scope of operations, defectivity inspections are critical for sustaining high yield levels of products. The novel dispatching strategy guides operators in selecting lots that will later be controlled in defectivity. Results show that the system is effective since the impact of measures has improved and the Wafer at Risk on process tools has been reduced. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/CoASE.2012.6386374 | Automation Science and Engineering |
Keywords | Field | DocType |
inspection,integrated circuit manufacture,manufacturing processes,risk management,complex manufacturing process,defectivity inspections,dispatching strategy guides operators,lot dispatching strategy,process tools,semiconductor manufacturing,wafers | Wafer,Semiconductor device fabrication,Manufacturing engineering,Risk management,Process control,Engineering,Manufacturing process | Conference |
ISSN | ISBN | Citations |
2161-8070 | 978-1-4673-0429-0 | 1 |
PageRank | References | Authors |
0.37 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gloria Rodríguez-Verján | 1 | 6 | 1.55 |
| Eric Tartiere | 2 | 1 | 0.37 |
| Jacques Pinaton | 3 | 19 | 12.98 |
| Stéphane Dauzère-Pérès | 4 | 740 | 65.50 |
| Alexis Thieullen | 5 | 1 | 0.37 |
| Rodriguez-Verjan, G. | 6 | 1 | 0.37 |
| Dauzere-Peres, S. | 7 | 5 | 1.22 |