Name
Abstract | ||
|---|---|---|
This paper presents an extension to a digital core-based test arhitecture to support testing of mixed-signal cores in a system-on-chip. It also presents a new mixed-signal test development flow that comprises a test library based approach to ease mixed-signal test development. The new flow was realized and experiments show clear advantages. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ITC.2004.75 | ITC |
Keywords | Field | DocType |
new flow,digital core-based test methodology,digital core-based test arhitecture,test library,support mixed-signal,mixed-signal test development,clear advantage,mixed-signal core,new mixed-signal test development,integrated circuit design,design for testability,system on chip | Boundary scan,Design for testing,Automatic test pattern generation,Test method,Computer architecture,Automatic test equipment,Computer science,Circuit extraction,Electronic engineering,Application-specific integrated circuit,Mixed-signal integrated circuit | Conference |
ISSN | ISBN | Citations |
1089-3539 | 0-7803-8581-0 | 2 |
PageRank | References | Authors |
0.45 | 5 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Geert Seuren | 1 | 2 | 0.79 |
| Tom Waayers | 2 | 128 | 11.47 |