Name
Abstract | ||
|---|---|---|
A clock and data recovery (CDR) circuit using a new half-rate wide-range phase detection technique has been developed. Unlike the conventional three-state phase detectors, the proposed detector is applicable to the Non-Retum-to-Zero (NRZ) data stream and also has low jitter and wide capture range characteristics. The CDR circuit was implemented in a 0.35-mu m N-well CMOS technique. Experimental results demonstrate that it can achieve the peak-to-peak jitter of the recovered clock and the retimed data about 120 ps and 170 ps, respectively, while operating at the input data rate of 1 Gb/s. The total power dissipation of the CDR is 64.8 mW for the supply 3 V. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1093/ietele/e89-c.6.746 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
phase-locked loop, phase synchronization, clock and data recovery, phase detector | Phase-locked loop,Clock recovery,Half Rate,Phase synchronization,CMOS,Electronic engineering,Jitter,Phase detector,Engineering,Detector | Journal |
Volume | Issue | ISSN |
E89C | 6 | 1745-1353 |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ching-Yuan Yang | 1 | 227 | 36.15 |
| Yu Lee | 2 | 11 | 3.21 |
| Cheng-hsing Lee | 3 | 0 | 0.34 |