Name
Abstract | ||
|---|---|---|
For performance-critical microprocessors, efficient test-selection methods are needed for reusing a subset of functional validation tests to detect manufacturing defects. Our new input/output transition fault-coverage metric (TRIO) at the register-transfer level is shown to perform much better than current metric in test selection at only an incrementally higher computational cost. TRIO may also be used for testability analysis early in the design cycle. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/VTS.2007.30 | VTS |
Keywords | Field | DocType |
performance-critical microprocessors,efficient test-selection method,register-transfer level,efficient rtl coverage metric,design cycle,output transition fault-coverage metric,functional test selection,testability analysis,functional validation test,new input,computational cost,test selection,manufacturing,fault coverage,design for testability,logic,computational modeling,input output,register transfer level,functional testing | Design for testing,Test selection,Computer science,Reuse,Real-time computing,Functional validation,Electronic engineering,Testability analysis,Test compression,Reliability engineering,Design cycle | Conference |
ISSN | ISBN | Citations |
1093-0167 | 0-7695-2812-0 | 8 |
PageRank | References | Authors |
0.53 | 17 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jian Kang | 1 | 8 | 0.53 |
| Sharad C. Seth | 2 | 671 | 93.61 |
| Vijay Gangaram | 3 | 35 | 4.16 |