Paper Info
Title
A low-power direct digital frequency synthesizer using an analogue-sine-conversion technique
Abstract
A new approach for d irect digital frequency synthesizer (DDFS) with analogue sine conversion is presented. The proposed DDFS adopts the ROM-less architecture with linear DAC to achieve higher speed operation and lower power consumption. Fabricated by 0.18-μm CMOS process, the DDFS employs a 9-bits pipe line accumulator to provide an 8-bits amplitude resolution for the DAC circuit. At 1-GHz clock frequency, the power consumption is 50 mw at 1. 8-V power supply and the spurious free dynamic range (SFDR) is 44 dBc at the N yquist synthesized frequency. The total chip area is 0.52 mm2.
Year
DOI
Venue
2011
10.1109/ISLPED.2011.5993635
ISLPED
Keywords
Field
DocType
nyquist synthesized frequency,direct digital frequency synthesizer,cmos process,rom-less architecture,dac circuit,power consumption,word length 8 bit,low-power direct digital frequency synthesizer,analogue-digital conversion,1-ghz clock frequency,8-bits amplitude resolution,power 50 mw,word length 9 bit,voltage 1.8 v,sfdr,size 0.18 mum,pipe line accumulator,power supply,direct digital synthesis,cmos digital integrated circuits,dac,low-power direct digital frequency,frequency 1 ghz,direct digital frequency synthesizer (ddfs),analogue-sine-conversion,proposed ddfs,lower power consumption,analogue-sine-conversion technique,linear dac,ddfs,cmos integrated circuits,chip,read only memory,frequency synthesizer,switches,adders,spurious free dynamic range
Adder,Computer science,Spurious-free dynamic range,Chip,CMOS,Electronic engineering,dBc,Direct digital synthesizer,Electrical engineering,Accumulator (structured product),Clock rate
Conference
ISSN
ISBN
Citations 
Pending E-ISBN : 978-1-61284-659-0
978-1-61284-659-0
1
PageRank 
References 
Authors
0.41
2
3
Name
Order
Citations
PageRank
Jun-Hong Weng1163.77
Ching-Yuan Yang222736.15
Yi-Lin Jhu310.41