Name
Abstract | ||
|---|---|---|
Diagnosis of scan test fail data plays a crucial role in enhancing ramp up of new CMOS technology generations. To enable faster feedback it is preferable to establish a monitoring diagnosis methodology on the production test floor. This paper reports results of a study on using test time optimized compressed scan technology and associated new algorithms for fault diagnosis. Data is based on a system-on-a-chip (SoC) product that is manufactured using Infineon Technologies' 130 nm process. A comparison with uncompressed scan test and diagnosis shows feasibility of implementing a monitoring diagnosis flow with compressed scan test serving the high throughput test flow. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/TEST.2005.1583972 | ITC |
Keywords | Field | DocType |
automatic test equipment,high throughput,statistics,automatic test pattern generation,cmos integrated circuits,system on a chip,cmos technology,system on chip,statistical analysis,failure analysis | Compression (physics),Automatic test pattern generation,System on a chip,Automatic test equipment,Computer science,Electronic engineering,Real-time computing,CMOS,Throughput,Test compression,Uncompressed video | Conference |
Citations | PageRank | References |
22 | 1.42 | 11 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Andreas Leininger | 1 | 43 | 3.88 |
| Peter Muhmenthaler | 2 | 22 | 2.78 |
| Wu-tung Cheng | 3 | 1350 | 121.45 |
| Nagesh Tamarapalli | 4 | 772 | 58.83 |
| Wu Yang | 5 | 26 | 3.18 |
| Hans Tsai | 6 | 22 | 1.42 |