Paper Info
Title
Design of asynchronous circuits for high soft error tolerance in deep submicrometer CMOS circuits
Abstract
As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits for high soft error tolerance. We analyze the behavior of null convention logic (NCL) circuits in the presence of particle strikes, and propose an asynchronous pipeline for soft-error correction and a novel technique to improve the robustness of threshold gates, which are basic components in NCL, against particle strikes by using Schmitt trigger circuit and resizing the feedback transistor. Experimental results show that the proposed threshold gates do not generate soft errors under the strike of a particle within a certain energy range if a proper transistor size is applied. The penalties, such as delay and power consumption, are also presented
Year
DOI
Venue
2010
10.1109/TVLSI.2008.2011554
IEEE Trans. VLSI Syst.
Keywords
Field
DocType
index terms,feedback transistor,asynchronous circuit,deep submicrometer cmos circuit,high soft error tolerant,particle strike,combinational logic,asynchronous pipeline,high soft error tolerance,conventional soft error tolerant,null convention logic,soft error,schmitt trigger circuit,pipelines,logic circuits,combinational circuits,robustness
Logic gate,Digital electronics,Soft error,Computer science,Schmitt trigger,CMOS,Combinational logic,Real-time computing,Electronic engineering,Electronic circuit,Asynchronous circuit
Journal
Volume
Issue
ISSN
18
3
1063-8210
Citations 
PageRank 
References 
13
0.85
18
Authors
4
Name
Order
Citations
PageRank
Weidong Kuang1706.95
Peiyi Zhao2969.81
J. S. Yuan3130.85
R. F. DeMara452870.33