Name
Abstract | ||
|---|---|---|
The Scalable Communications Core (SCC) is a power- and area-efficient solution for physical layer (PHY) and lower MAC processing of concurrent multiple wireless protocols. Our architecture consists of coarse-grained, heterogeneous, programmable accelerators ... |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ISVLSI.2007.5 | ISVLSI |
Keywords | Field | DocType |
lower mac processing,physical layer,hash-based approach,concurrent multiple wireless protocol,logic synthesis,functional regularity extraction,area-efficient solution,scalable communications core,programmable accelerator,phase detection,clustering algorithms,high level synthesis,cryptography,minimization,physical design,logic circuits,design for manufacture,logic design,manufacturing,logic level | Logic synthesis,Netlist,Logic gate,Logic optimization,Computer science,High-level synthesis,Theoretical computer science,Logic level,Hash function,Design for manufacturability | Conference |
ISSN | ISBN | Citations |
2159-3469 | 0-7695-2896-1 | 6 |
PageRank | References | Authors |
0.47 | 16 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Angelo P. E. Rosiello | 1 | 6 | 0.47 |
| Fabrizio Ferrandi | 2 | 548 | 56.95 |
| Davide Pandini | 3 | 94 | 15.76 |
| D. Sciuto | 4 | 1720 | 176.61 |