Name
Abstract | ||
|---|---|---|
With each CMOS technology generation, leakage energy has been increasing at an exponential rate and hence, managing the energy consumption of large, last-level caches is becoming a critical research issue in modern chip design. Saving cache energy in QoS systems is especially challenging, since, to avoid missing deadlines, a suitable balance needs to be made between energy saving and performance loss. We present CASHIER, a Cache Energy Saving Technique for Quality of Service Systems. Cashier uses dynamic profiling to estimate the memory subsystem energy and execution time of the program under multiple last level cache (LLC) configurations. It then reconfigures LLC to an energy efficient configuration with a view to meet the deadline. In QoS systems, allowed slack may be specified either as percentage of baseline execution time or as absolute slack and Cashier can work for both these cases. The experiments show the effectiveness of Cashier in saving cache energy. For example, for an L2 cache size of 2MB and 5% allowed-slack over baseline, the average saving in memory subsystem energy by using Cashier is 23.6%. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/VLSID.2013.160 | VLSI Design |
Keywords | Field | DocType |
l2 cache size,last-level cache,cache energy saving technique,leakage energy,energy efficient configuration,qos system,energy saving,energy consumption,cache energy,average saving,qos systems,memory subsystem energy,cmos integrated circuits,quality of service | Cache pollution,Computer science,Cache,CPU cache,Cache algorithms,Real-time computing,Page cache,Cache coloring,Smart Cache,Energy consumption,Operating system,Embedded system | Conference |
ISSN | Citations | PageRank |
1063-9667 | 13 | 0.50 |
References | Authors | |
18 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sparsh Mittal | 1 | 817 | 50.36 |
| Zhao Zhang | 2 | 79 | 7.53 |
| Ya-nan Cao | 3 | 131 | 19.42 |