Name
Abstract | ||
|---|---|---|
Dynamic laser stimulation (DLS) techniques based on operating integrated circuits (ICs) become a standard failure analysis technique for soft defect localization. This type of defect is getting more and more common with advanced technology; therefore, DLS is becoming a key technique for defect localization. To perform this technique, the determination of a pass–fail border in shmoo plot is necessary. It is essential to know the impact of the defect on the shmoo plot shape with different defects. This paper presents shmoos plots simulation for common defects encountered in ICs failure analysis. Ability of DLS to detect defects according to their resistances and capacitances values are clearly established. In the second part of this paper, case studies which validate simulations results are presented. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1016/j.microrel.2008.07.043 | Microelectronics Reliability |
Keywords | Field | DocType |
failure analysis,integrated circuit | Shmoo plot,Capacitance,CMOS,Electronic engineering,Engineering,Miniaturization,Integrated circuit,Electrical engineering | Journal |
Volume | Issue | ISSN |
48 | 8 | 0026-2714 |
Citations | PageRank | References |
3 | 0.83 | 2 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. Machouat | 1 | 4 | 1.65 |
| G. Haller | 2 | 3 | 0.83 |
| Vincent Goubier | 3 | 6 | 2.80 |
| D. Lewis | 4 | 12 | 3.76 |
| P. Perdu | 5 | 60 | 27.38 |
| V. Pouget | 6 | 51 | 11.38 |
| Pascal Fouillat | 7 | 58 | 14.00 |
| F. Essely | 8 | 4 | 1.95 |