Paper Info
Title
On Testability of Multiple Precharged Domino Logic
Abstract
Domino circuits are increasingly popular because they offer a significant performance boost over static ones. An inherent problem with domino CMOS gates is that under specific input conditions the charge redistribution between parasitic capacitances at internal nodes of the circuit can destroy the noise margin and cause glitches at the output of a domino gate.Among the dominant solutions proposed, in the open literature, to overcome this problem is the technique of internal nodes multiple precharging. However the added precharge transistors are not testable for stuck-open and stuck-on faults. Undetectable stuck-open faults on these transistors cause reduction of the noise margins of the gate. Then the operation of the circuit in the field is sensitive to environmental factors, such as noise. In this paper we propose a new internal nodes multiple precharging scheme that leads to testable designs for stuck-open and stuck-on faults.
Year
DOI
Venue
2000
10.1109/ISQED.2000.838886
San Jose, CA
Keywords
Field
DocType
undetectable stuck-open fault,noise margin,multiple precharging,multiple precharged domino logic,internal node,new internal node,inherent problem,domino gate,domino cmos gate,stuck-on fault,domino circuit,capacitance,glitches,semiconductor device modeling,informatics,logic gates,testability
Domino logic,Testability,Glitch,Logic gate,Semiconductor device modeling,Computer science,Real-time computing,Electronic engineering,CMOS,Domino,Noise margin,Electrical engineering
Conference
ISBN
Citations 
PageRank 
0-7695-0525-2
0
0.34
References 
Authors
2
4
Name
Order
Citations
PageRank
Th. Haniotakis1437.74
Y. Tsiatouhas26811.07
D. Nikolos329131.38
Efstathiou, C.400.68