Name
Abstract | ||
|---|---|---|
Cache bandwidth and reliability are both of great importance for microprocessor design. Recently, the replication cache has been proposed to enhance data cache reliability against soft errors. The replication cache is a small fully associative cache to store the replica(s) for every write to the L1 data cache. In addition to enhancing reliability, this paper proposes to make use of the replication cache in order to improve the performance of multiple-issue superscalar microprocessors by enlarging the cache read bandwidth effectively. Our experimental results show that exploiting a replication cache with only 8 entries can improve the performance of a 4-issue superscalar microprocessor by 9.4% on average without compromising the enhanced data integrity.
|
Year | DOI | Venue |
|---|---|---|
2006 | 10.1145/1147349.1147356 | ACM Sigarch Computer Architecture News |
Keywords | Field | DocType |
temporal locality | Cache invalidation,Cache pollution,Computer science,Cache,MESI protocol,Parallel computing,Page cache,Real-time computing,Cache algorithms,Cache coloring,Smart Cache | Journal |
Volume | Issue | ISSN |
34 | 1 | 0163-5964 |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| B. Allu | 1 | 0 | 0.34 |
| Wei Zhang | 2 | 163 | 11.75 |
| M. Kandala | 3 | 0 | 0.34 |