Name
Abstract | ||
|---|---|---|
In this paper a new class of highly parameterizable coarse-grained reconfigurable architectures called weakly programmable processor arrays is discussed. The main advantages of the proposed architecture template are the possibility of partial and differential reconfiguration and the systematical classification of different architectural parameters which allow to trade-off flexibility and hardware cost The applicability of our approach is tested in a case study with different interconnect topologies on an FPGA platform. The results show substantial flexibility gains with only marginal additional hardware cost. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/FPT.2006.270293 | 2006 IEEE INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY, PROCEEDINGS |
Keywords | Field | DocType |
field programmable gate arrays,parallel processing | Computer architecture,Architecture,Computer science,Parallel processing,Parallel computing,Field-programmable gate array,Network topology,Interconnection,Control reconfiguration,Embedded system | Conference |
Citations | PageRank | References |
40 | 2.35 | 8 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dmitrij Kissler | 1 | 78 | 7.30 |
| Frank Hannig | 2 | 595 | 75.66 |
| Alexey Kupriyanov | 3 | 79 | 6.40 |
| Jürgen Teich | 4 | 2886 | 273.54 |