Name
Title | ||
|---|---|---|
Analysis Of Operation Margin And Read Speed In 6t-And 8t-Sram With Local Electron Injected Asymmetric Pass Gate Transistor |
Abstract | ||
|---|---|---|
Three types of electron injection scheme: both side injection scheme and self-repair one side injection scheme Type A (injection for once) and Type B (injection for twice) are proposed and analyzed comprehensively for 65 nm technology node 6T- and 8T-SRAM cells to find the optimum injection scheme and cell architecture. It is found that the read speed degrades by as much as 6.3 times in the 6T-SRAM with the local injected electrons. However, the read speed of the 8T-SRAM cell does not degrade because the read port is separated from the write pass gate transistors. Furthermore, the self-repair one side injection scheme is most suitable to solve the conflict of the half select disturb and write characteristics. The worst cell characteristics of Type A and Type B self-repair one side injection schemes were found to be the same. In the self-repair one side injection 8T-SRAM, the disturb margin increases by 141% without write margin or read speed degradation. The proposed schemes have no process or area penalty compared with the standard CMOS-process. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1587/transele.E95.C.564 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
6T/8T-SRAM, asymmetric pass gate transistor, local electron injection, disturb/write margin, read speed | Electron injection,Electronic engineering,Static random-access memory,Pass gate,Engineering,Transistor,Electrical engineering,Write margin,Electron | Journal |
Volume | Issue | ISSN |
E95C | 4 | 1745-1353 |
Citations | PageRank | References |
1 | 0.36 | 5 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kousuke Miyaji | 1 | 59 | 9.73 |
| Kentaro Honda | 2 | 60 | 9.67 |
| Shuhei Tanakamaru | 3 | 121 | 18.35 |
| Shinji Miyano | 4 | 85 | 12.63 |
| Ken Takeuchi | 5 | 46 | 9.13 |