| Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory. | 0 | 0.34 | 2016 |
| Understanding the Relation Between the Performance and Reliability of nand Flash/SCM Hybrid Solid-State Drive. | 0 | 0.34 | 2016 |
| Variation Of Scm/Nand Flash Hybrid Ssd Performance, Reliability And Cost By Using Different Ssd Configurations And Error Correction Strengths | 0 | 0.34 | 2016 |
| Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage | 2 | 0.37 | 2015 |
| Reliability enhancement of 1Xnm TLC for cold flash and millennium memories | 1 | 0.36 | 2015 |
| Privacy-protection solid-state storage (PP-SSS) system: Automatic lifetime management of internet-data's right to be forgotten | 1 | 0.37 | 2015 |
| 7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage | 3 | 0.44 | 2015 |
| A Design Strategy Of Error-Prediction Low-Density Parity-Check (Ep-Ldpc) Error-Correcting Code (Ecc) And Error-Recovery Schemes For Scaled Nand Flash Memories | 3 | 0.48 | 2015 |
| Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs) | 2 | 0.38 | 2015 |
| NAND Flash Memory/ReRAM Hybrid Unified Solid-State-Storage Architecture | 6 | 0.50 | 2014 |
| 19.6 Hybrid storage of ReRAM/TLC NAND Flash with RAID-5/6 for cloud data centers | 6 | 0.71 | 2014 |
| Application-aware solid-state drives (SSDs) with adaptive coding | 7 | 1.00 | 2014 |
| Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs) | 20 | 1.03 | 2013 |
| Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme | 2 | 0.43 | 2013 |
| Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications | 5 | 1.28 | 2013 |
| Analysis Of Operation Margin And Read Speed In 6t-And 8t-Sram With Local Electron Injected Asymmetric Pass Gate Transistor | 1 | 0.36 | 2012 |
| Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme. | 25 | 2.91 | 2012 |
| Highly Reliable, High Speed And Low Power Nand Flash Memory-Based Solid State Drives (Ssds) | 3 | 0.54 | 2012 |
| 95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm. | 20 | 4.56 | 2011 |
| A 0.5 V Operation Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems | 0 | 0.34 | 2011 |
| Improvement of Read Margin and Its Distribution by VTH Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection. | 6 | 0.59 | 2011 |
| Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor | 8 | 0.73 | 2010 |
