Name
Abstract | ||
|---|---|---|
We propose two eight-neighbor, two five-nearest-neighbor, and three six-nearest-neighbor interconnection topologies for many-core processor arrays-three of which use five-sided or hexagonal processor tiles-which typically reduce application communication distance and result in an overall application processor that requires fewer cores and lower power consumption. A 16-bit processor with the appropriate number of input and output ports is implemented in all topologies and tile shapes. The hexagonal and five-sided processor tiles and arrays of tiles are laid out with industry standard automatic place and route design flow and Manhattan-style wires without full-custom layout. A 1080p H.264/AVC residual video encoder and a 54 Mb/s 802.11a/g OFDM wireless local area network baseband receiver are mapped onto all topologies. The six-neighbor hexagonal tile incurs a 2.9% area increase per tile compared with the four-neighbor 2-D mesh, but its much more effective interprocessor interconnect yields an average total application area reduction of 22% and an average application power savings of 17%. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TVLSI.2013.2265937 | IEEE Transactions on Very Large Scale Integration Systems |
Keywords | Field | DocType |
route design flow,interconnection topology,communication distance,network routing,power consumption,hexagonal processor,multiprocessor interconnection networks,digital signal processing (dsp),processor tile shapes,bit rate 54 mbit/s,nearest-neighbor interconnection topologies,multimedia,low-power electronics,manhattan-style wires,2d mesh,many-core processor arrays,five-sided processor tiles,many-core processor,power savings,integrated circuit design,interprocessor interconnect,cmos digital integrated circuits,radio receivers,storage capacity 16 bit,802.11a/g ofdm wireless local area network baseband receiver,network on chip (noc).,dense on-chip networks,wireless lan,interconnect topologies,hexagonal processor tiles,network-on-chip,network on chip (noc),h.264/avc residual video encoder,video codecs,low power electronics,network on chip | Media processor,Network processor,Baseband,Computer science,Place and route,Network topology,Electronic engineering,Encoder,Interconnection,Tile | Journal |
Volume | Issue | ISSN |
22 | 6 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 9 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhibin Xiao | 1 | 22 | 4.85 |
| Bevan M. Baas | 2 | 295 | 27.78 |