Name
Abstract | ||
|---|---|---|
This work presents a low-power dual-edge triggered static scanable flip-flop that uses reduced swing-clock and -data to manage
dynamic power. The circuit employs clock- and power-gating during idle mode to eliminate dynamic power and reduce static power,
while retaining circuit’s state. The static structure of the circuit makes it feasible to be employed in variable frequency
power control designs. HSPICE post-layout simulation conducted for 90nm CMOS technology showed that in terms of power-delay
product, device count, and leakage power the proposed design is comparable to other high performance static flip-flops.
|
Year | DOI | Venue |
|---|---|---|
2009 | 10.1007/978-3-642-11802-9_20 | Workshop on Power and Timing Modeling, Optimization and Simulation |
Keywords | Field | DocType |
static structure,static power,low-power flip-flop,device count,static flip-flop,variable frequency power control,test.,leakage power,state retention,hspice post-layout simulation,static scanable flip-flop,dynamic power,cmos technology,low-power dual-edge,power control,test | Computer science,Idle,Power control,Volt-ampere,Power factor,Real-time computing,CMOS,Electronic engineering,Dynamic demand,Flip-flop,Switched-mode power supply | Conference |
Volume | ISSN | ISBN |
5953 | 0302-9743 | 3-642-11801-1 |
Citations | PageRank | References |
0 | 0.34 | 13 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hossein Karimiyan Alidash | 1 | 2 | 1.43 |
| Sayed Masoud Sayedi | 2 | 47 | 9.88 |
| Hossein Saidi | 3 | 131 | 20.73 |