Title
A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores
Abstract
This paper presents a secure test wrapper (STW) design that is compatible with the IEEE 1500 standard. STW protects not only internal scan chains but also primary inputs and outputs, which may contain critical information (such as encryption keys) during the system operation. To reduce the STW area, flip-flops in the wrapper boundary cells also serve as the LFSR to generate the golden key. Experimental results on an AES core show that STW provides very high security at the price of only 5% area overhead with respect to the original IEEE 1500 test wrapper.
Year
DOI
Venue
2012
10.1109/TVLSI.2010.2089071
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Keywords
Field
DocType
embedded cores,secure test wrapper,security,test wrapper,design for testability,ieee 1500 standard,boundary scan attacks,secure test wrapper design,scan,encryption key,stw area,critical information,wrapper boundary cell,area overhead,aes core show,original ieee,internal scan attacks,discrete fourier transform,system on a chip,encryption,security testing,registers
Design for testing,Boundary scan,Linear feedback shift register,Boundary cell,System on a chip,Computer science,Encryption,Real-time computing,Embedded system
Journal
Volume
Issue
ISSN
20
1
1063-8210
Citations 
PageRank 
References 
20
1.06
17
Authors
2
Name
Order
Citations
PageRank
Geng-Ming Chiu1211.45
James Chien-Mo Li218727.16