Paper Info
Title
POD: A 3D-Integrated Broad-Purpose Acceleration Layer
Abstract
To build a future many-core processor, industry must address the challenges of energy consumption and performance scalability. A 3D-integrated broad-purpose accelerator architecture called parallel-on-demand (POD) integrates a specialized SIMD-based die layer on top of a CISC superscalar processor to accelerate a variety of data-parallel applications. It also maintains binary compatibility and facilitates extensibility by virtualizing the acceleration capability.
Year
DOI
Venue
2008
10.1109/MM.2008.58
IEEE Micro
Keywords
Field
DocType
broad-purpose acceleration layer,broad-purpose accelerator architecture,parallel-on-demand architecture,cisc superscalar processor,microprocessor chips,performance scalability,simd-based die layer,parallel architectures,low-power electronics,future many-core processor,acceleration capability virtualization,many-core processor,logic design,specialized simd-based die layer,parallel simd designs,data-parallel application,energy consumption,data-parallel applications,facilitates extensibility,binary compatibility,parallel machines,pod 3d-integrated broad-purpose accelerator architecture,acceleration capability,pipelines,multicore,acceleration,out of order,low power electronics
Computer architecture,Computer science,Parallel computing,SIMD,Binary code compatibility,Complex instruction set computing,Out-of-order execution,Extensibility,Energy consumption,Multi-core processor,Embedded system,Scalability
Journal
Volume
Issue
ISSN
28
4
0272-1732
Citations 
PageRank 
References 
8
1.35
8
Authors
5
Name
Order
Citations
PageRank
Dong Hyuk Woo157629.55
Hsien-Hsin Sean Lee21657102.66
Joshua Bruce Fryman3807.19
Allan D. Knies4122.47
Marsha Eng5394.58