Name
Title | ||
|---|---|---|
Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor |
Abstract | ||
|---|---|---|
The growing importance of post-silicon validation in ensuring functional correctness of high-end designs has increased the need for synergy between the pre-silicon verification and post-silicon validation. This synergy starts with a common verification plan. It continues with common verification goals and shared tools and techniques. This paper describes our experience in improving this synergy in the pre- and post-silicon verification of IBM's POWER7 processor chip and by leveraging pre-silicon methodologies and techniques in the post-silicon validation of the chip. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/2024724.2024856 | DAC |
Keywords | Field | DocType |
high-end designs,post-silicon validation,pre-silicon verification resource,functional correctness,microprocessor chips,ibm power7 processor chip,common verification goal,coverage,pre-silicon verification resources,pre-silicon verification,silicon,synergy,pre-silicon methodology,si,functional verification,elemental semiconductors,high-end design,post-silicon verification,stimuli generation,ibm power7 processor,power7 processor chip,common verification plan,computer bugs,generators,aging,acceleration,post silicon validation,chip,observability | IBM,Functional verification,Post-silicon validation,Computer science,Intelligent verification,Correctness,Software bug,Real-time computing,Verification,Electronic engineering,Embedded system,Software verification | Conference |
ISSN | ISBN | Citations |
0738-100x | 978-1-4503-0636-2 | 11 |
PageRank | References | Authors |
0.67 | 11 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| allon adir | 1 | 231 | 19.33 |
| Amir Nahir | 2 | 172 | 14.84 |
| G. Shurek | 3 | 285 | 42.50 |
| Avi Ziv | 4 | 465 | 72.49 |
| Charles Meissner | 5 | 40 | 2.70 |
| J. Schumann | 6 | 88 | 4.20 |