Title
Effects of High-Level Discrete Signal Transform Formulations on Partitioning for Multi-FPGA Architectures
Abstract
The achievement of effective implementations to multi-FPGA architectures is greatly dependent on the process of partitioning. Although several automated high-level partitioning (HLP) methods have been reported [2], most of them are designed to solve general partitioning problems, and tend to apply generic local optimization techniques that miss out on alternate formulations that become apparent only with knowledge of the algorithm's functionality. The algorithmic formulation of discrete signal transforms (DST), especially that of the DFT, has been extensively studied. Automated computational algebra platforms for the algorithmic manipulation of fast transform algorithms have been proposed, as well as automated methods to optimize DST implementations to general purpose processor platforms [1]. However, these methods have yet to be successfully adapted to automated partitioning methodologies for dedicated distributed hardware platforms.
Year
DOI
Venue
2006
10.1109/FCCM.2006.38
FCCM
Keywords
Field
DocType
computer algebra,space exploration,topology,field programmable gate arrays,cost effectiveness,hardware,kronecker product,algebra,algorithm design and analysis,computer architecture
Discrete-time signal,General purpose,Computer science,Parallel computing,Computational algebra,Field-programmable gate array,Implementation,Local search (optimization)
Conference
ISBN
Citations 
PageRank 
0-7695-2661-6
0
0.34
References 
Authors
2
3
Name
Order
Citations
PageRank
Rafael A. Arce-Nazario1135.18
Manuel Jiménez2206.31
Domingo Rodríguez3208.03