| Evaluating the JEDEC Standard JEP173, Dynamic RDSON Test Method for GaN HEMTs | 0 | 0.34 | 2020 |
| An Error Analysis Model for Floating-Point DFT Algorithms | 0 | 0.34 | 2018 |
| An FPGA-based algorithm development framework for estimating the accuracy of embedded DSP signal transforms | 0 | 0.34 | 2017 |
| Adherence of a high-speed RRP LDMOS characterization setup to JESD 24-10 standard | 0 | 0.34 | 2017 |
| Embedded FFT hardware algorithm development using automated bi-dimensional scalable folding | 0 | 0.34 | 2017 |
| Statistical accuracy analysis of complex floating point multipliers | 1 | 0.40 | 2017 |
| A synchronous distance education hybrid model of college-level credits for high-school students. | 0 | 0.34 | 2016 |
| Automated characterization of reverse recovery parameters in high speed LDMOS devices | 0 | 0.34 | 2016 |
| A virtual instrument design for low-cost charge-pumping characterization of integrated MOSFETs | 1 | 0.48 | 2015 |
| Parametric DC and noise measurements in a unified test & characterization software tool framework | 0 | 0.34 | 2012 |
| Architectural Model and Resource Estimation for Distributed Hardware Implementation of Discrete Signal Transforms | 0 | 0.34 | 2008 |
| Mapping of Discrete Cosine Transforms onto Distributed Hardware Architectures | 3 | 0.48 | 2008 |
| Behavioral Modeling Methods for Switched-Capacitor Σ∆ Modulators. | 15 | 1.24 | 2007 |
| High-Level Partitioning of Discrete Signal Transforms for Multi-FPGA Architectures | 0 | 0.34 | 2006 |
| Effects of High-Level Discrete Signal Transform Formulations on Partitioning for Multi-FPGA Architectures | 0 | 0.34 | 2006 |
