Name
Abstract | ||
|---|---|---|
This paper discusses practical issues involved in applyinglogic built-in self-test (BIST) to four large industrialdesigns. These multi-clock designs, ranging in size from200K to 800K gates, pose significant challenges to logicBIST methodology, flow, and tools. The paper presents theprocess of generating a BIST-compliant core along with thelogic BIST controller for at-speed testing. Comparativedata on fault grades and area overhead between automatictest pattern generation (ATPG) and logic BIST arereported. The experimental results demonstrate that withautomation of the proposed solutions, logic BIST canachieve test quality approaching that of ATPG with minimalarea overhead and few changes to the design flow. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/TEST.1999.805650 | ITC |
Keywords | Field | DocType |
design flow,at-speed testing,thelogic bist controller,case studies,automatictest pattern generation,logic bist arereported,minimalarea overhead,area overhead,real issues,large industrial designs,applyinglogic built-in self-test,bist-compliant core,logic bist canachieve test,logic bist,industrial design,logic design,computer aided software engineering,design for testability,automatic test pattern generation,fault coverage,manufacturing,design methodology | Logic synthesis,Design for testing,Automatic test pattern generation,Fault coverage,Computer science,Automation,Real-time computing,Design flow,Electronic engineering,AND gate,Built-in self-test | Conference |
ISBN | Citations | PageRank |
0-7803-5753-1 | 173 | 17.93 |
References | Authors | |
8 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Graham Hetherington | 1 | 347 | 24.55 |
| Tony Fryars | 2 | 511 | 29.64 |
| Nagesh Tamarapalli | 3 | 772 | 58.83 |
| Mark Kassab | 4 | 654 | 48.74 |
| Abu S. M. Hassan | 5 | 265 | 32.29 |
| Janusz Rajski | 6 | 2460 | 201.28 |