Title
An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example.
Abstract
This work presents the first case of using the pseudoexhaustive testing (PET) for high-speed high-order (>;32 -bit) adders. It is shown that all single stack-at faults are detected by a pseudoexhaustive test set of 54 K patterns, compared to 264×2 patterns in the past. Also, all transition faults are detected by a pseudoexhaustive test set of 13 M patterns, compared to 264×4 patterns in the past. ...
Year
DOI
Venue
2012
10.1109/TCSI.2012.2206503
IEEE Transactions on Circuits and Systems I: Regular Papers
Keywords
Field
DocType
Adders,Circuit faults,Clocks,Positron emission tomography,Testing,Delay,Strontium
Adder,Latency (engineering),Computer science,Speed test,Electronic engineering,CMOS,Domino,Carry-save adder,Serial binary adder,Test set
Journal
Volume
Issue
ISSN
59
8
1549-8328
Citations 
PageRank 
References 
1
0.46
15
Authors
4
Name
Order
Citations
PageRank
Yu-shun Wang114031.90
Min-Han Hsieh273.69
James Chien-Mo Li318727.16
Charlie Chung-Ping Chen41396137.82