Name
Abstract | ||
|---|---|---|
In chip-multiprocessor (CMP) designs, limited memory bandwidth is a potential bottleneck of the system performance. New memory technologies, such as spin-torque-transfer memory (STT-RAM), resistive memory (RRAM), and embedded DRAM (eDRAM), are promising on-chip memory solutions for CMPs. In this paper, we propose a bandwidth-aware re-configurable cache hierarchy (BARCH) with hybrid memory technologies. BARCH consists of a hybrid cache hierarchy, a reconfiguration mechanism, and a statistical prediction engine. Our hybrid cache hierarchy chooses different memory technologies to configure each level so that the bandwidth provided by the overall hierarchy is optimized. Furthermore, we present a reconfiguration mechanism to dynamically adapt the cache space of each level based on the predicted bandwidth demands of different applications, which is guaranteed by our prediction engine. We evaluate the system performance gain obtained by our method with a set of multithreaded and multiprogrammed applications. Compared to traditional SRAM-based cache designs, our proposed design improves the system throughput by 58% and 14% for multithreaded and multiprogrammed applications, respectively.
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Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ICCAD.2011.6105304 | ICCAD |
Keywords | Field | DocType |
spin-torque-transfer memory,bandwidth-aware reconfigurable cache design,microprocessor chips,bandwidth-aware reconfigurable cache hierarchy,cache storage,barch,resistive memory,reconfigurable architectures,multi-threading,system performance,statistical prediction engine,hybrid memory technology,different memory technology,dram chips,limited memory bandwidth,hybrid cache hierarchy,multiprogrammed application,sram-based cache design,reconfiguration mechanism,memory bandwidth,chip-multiprocessor design,new memory technology,multithreaded application,embedded dram,on-chip memory solution,multi threading,chip,multiview video coding,motion estimation | Cache-oblivious algorithm,Cache pollution,Cache,Computer science,CPU cache,Cache-only memory architecture,Cache algorithms,Real-time computing,Cache coloring,Non-uniform memory access,Embedded system | Conference |
ISSN | ISBN | Citations |
1092-3152 E-ISBN : 978-1-4577-1398-9 | 978-1-4577-1398-9 | 13 |
PageRank | References | Authors |
0.54 | 18 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jishen Zhao | 1 | 638 | 38.51 |
| Cong Xu | 2 | 1154 | 48.25 |
| Yuan Xie | 3 | 6430 | 407.00 |