Name
Abstract | ||
|---|---|---|
Heterogeneous multicore platform has been widely used in various areas to achieve both power efficiency and high performance. This paper proposes a FPGA implementation of a hardware scheduler supporting parallel dataflow execution on heterogeneous multicore platform. The scheduler has the capability to explore potential parallelism, leading to a high acceleration of dependence-aware applications. Given the reconfigurable characteristic of FPGA platform, our scheduler supports changing accelerators during runtime to increase the flexibility of the platform. We implement and optimize the scheduler on a state-of-art Xilinx Virtex-5 FPGA board, experimental results show that our scheduler is efficient at both performance and resources usage. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ISCAS.2013.6572071 | ISCAS |
Keywords | Field | DocType |
hardware scheduler,xilinx virtex-5 fpga board,parallel dataflow execution,power efficiency,platform flexibility,potential parallelism,fpga platform,fpga implementation,dependence-aware application,resource usage,heterogeneous multicore platform,field programmable gate arrays,reconfigurable characteristic,multicore processing,hardware | Electrical efficiency,Computer architecture,Computer science,FPGA prototype,Field-programmable gate array,Dataflow,Acceleration,Multi-core processor,Reconfigurable computing | Conference |
Volume | Issue | ISSN |
null | null | 0271-4302 |
ISBN | Citations | PageRank |
978-1-4673-5760-9 | 0 | 0.34 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Junneng Zhang | 1 | 97 | 8.85 |
| Chao Wang | 2 | 372 | 62.24 |
| Xi Li | 3 | 202 | 36.61 |
| Xuehai Zhou | 4 | 551 | 77.54 |