Name
Abstract | ||
|---|---|---|
This paper presents a 5-Gb/s clock and data recovery (CDR) circuit which implements a calibration circuit to correct static phase offsets in a linear phase detector. Static phase offsets directly reduce the performance of CDR circuits as the incoming data is not sampled at the center of the eye. Process nonidealities can cause static phase offsets in linear phase detectors by adversely affecting t... |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TCSI.2008.916400 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | Field | DocType |
Circuits,Phase detection,Detectors,Calibration,Clocks,Voltage-controlled oscillators,Semiconductor device measurement,Robustness,Silicon,Frequency | Clock signal,Linear phase,Computer science,Electronic engineering,CMOS,Phase detector,Electronic circuit,Detector,Calibration,Bit error rate | Journal |
Volume | Issue | ISSN |
55 | 3 | 1549-8328 |
Citations | PageRank | References |
6 | 0.71 | 3 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| David Rennie | 1 | 24 | 3.29 |
| Manoj Sachdev | 2 | 669 | 88.45 |