Paper Info
Title
Region-based routing: a mechanism to support efficient routing algorithms in NoCs
Abstract
An efficient routing algorithm is important for large on-chip networks [network-on-chip (NoC)] to provide the required communication performance to applications. Implementing NoC using table-based switches provide many advantages, including possibility of changing routing algorithms and fault tolerance, due to the option of table reconfigurations. However, table-based switches have been considered unsuitable for NoCs due to their perceived high area and power consumption. In this paper, we describe the region-based routing (RBR) mechanism which groups destinations into network regions allowing an efficient implementation with logic blocks. RBR can also be viewed as a mechanism to reduce the number of entries in routing tables. RBR is general and can be used in conjunction with any adaptive routing algorithm. In particular, we have evaluated the proposed scheme in conjunction with a general routing algorithm, namely segment-based routing (SR) and an Application Specific Routing Algorithm (APSRA) using regular and irregular mesh topologies. Our study shows that the number of entries in the table is significantly reduced, especially for large networks. Evaluation results show that RBR requires only four regions to support several routing algorithms in a 2-D mesh with no performance degradation. Considering link failures, our results indicate that RBR combined with SR is able to tolerate up to 7 link failures in an 8 × 8 mesh. RBR also reduces area and power dissipation of an equivalent table-based implementation by factors of 8 and 10, respectively. Moreover, the degradation in performance of the network is insignificant when using APSRA combined with RBR.
Year
DOI
Venue
2009
10.1109/TVSLSI.2008.2012010
IEEE Trans. VLSI Syst.
Keywords
Field
DocType
switches,network on a chip,throughput,degradation,network on chip,computer science,chip,routing algorithms,fault tolerant,adaptive routing,fault tolerance,algorithm design and analysis,strontium,network topology,routing,system on a chip,power dissipation
Multipath routing,Link-state routing protocol,Dynamic Source Routing,Static routing,Policy-based routing,Enhanced Interior Gateway Routing Protocol,Computer science,Computer network,Destination-Sequenced Distance Vector routing,Real-time computing,Routing table,Distributed computing
Journal
Volume
Issue
ISSN
17
3
1063-8210
Citations 
PageRank 
References 
35
1.29
31
Authors
7
Name
Order
Citations
PageRank
Andres Mejia11315.97
Maurizio Palesi2111978.82
José Flich326826.03
Shashi Kumar428216.58
Pedro López523316.39
Rickard Holsmark624913.10
José Duato73481294.85