Name
Abstract | ||
|---|---|---|
In traditional yield enhancement approaches, a lot of computation efforts have to be paid first to find the feasible regions and the Pareto fronts, which will become a heavy cost for large analog circuits. In order to reduce the computation efforts, this work tries to finish all iteration steps of the yield enhancement flow at behavior level. First, a novel force-directed nominal point moving (NPM) algorithm is proposed to find a better nominal point without building the feasible regions. Then, an equation-based behavior-level sizing approach is proposed to map the NPM results at performance level to behavior-level parameters. A fast behavior-level Monte Carlo simulation is also proposed to shorten the iterative yield enhancement flow. Finally, using the obtained behavioral parameters as the sizing targets of each sub-block, the device sizing time is significantly reduced instead of sizing from the system-level specifications directly. As demonstrated on a complex CPPLL design, this behavior-level approach could be another efficient methodology to help designers improve their analog circuits toward better yield. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1145/1837274.1837501 | DAC |
Keywords | Field | DocType |
large-scaled analog circuits,analogue integrated circuits,better yield,monte carlo simulation,traditional yield enhancement approach,computation effort,behavior-level approach,nominal point moving algorithm,equation-based behavior-level,process variation,monte carlo methods,integrated circuit design,iterative yield enhancement,integrated circuit yield,nominal point,feasible region,large-scaled analog circuit,behavior-level yield enhancement approach,analog circuits,iterative yield enhancement flow,behavior-level yield enhancement,sizing target,yield enhancement,fast behavior-level,pareto fronts,optimization,phase locked loops,principal component analysis,circuit topology,pareto front,analog computers,force,mathematical model,algorithm design and analysis | Monte Carlo method,Mathematical optimization,Analogue electronics,Computer science,Flow (psychology),Electronic engineering,Integrated circuit design,Sizing,Process variation,Pareto principle,Computation | Conference |
ISSN | ISBN | Citations |
0738-100X | 978-1-4244-6677-1 | 0 |
PageRank | References | Authors |
0.34 | 19 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chin-Cheng Kuo | 1 | 27 | 4.40 |
| Yen-Lung Chen | 2 | 24 | 4.59 |
| I-Ching Tsai | 3 | 1 | 0.71 |
| Li-Yu Chan | 4 | 0 | 0.34 |
| Chien-Nan Jimmy Liu | 5 | 97 | 27.07 |