Name
Abstract | ||
|---|---|---|
Networks on chip (NoCs) has a strong impact on overall chip performance. Interconnection bandwidth is limited by the critical path delay. Recent works show that the critical path includes the switch input buffer control logic. As a consequence, by removing buffers, switch clock frequency can be doubled. Recently, a new switching technique for NoCs called Blind Packet Switching (BPS) has been proposed. It is based on replacing the buffers of the switch ports by simple latches. Since buffers consume a high percentage of switch power and area, BPS not only improves performance but also helps in reducing power and area. In BPS there are no buffers at the switch ports, so packets can not be stopped. If the required output port is busy, the packet will be dropped. In order to prevent packet dropping, some techniques based on resource replication has been proposed. In this paper, we propose some alternative and complementary techniques that does not rely on resource replication. By using these techniques, packet dropping and its negative effects are highly reduced. In particular, packet dropping is completely removed for a very wide network traffic range. The first dropped packet appears at a 11.6 higher traffic load. As a consequence, network throughput is increased and the packet latency is kept almost constant. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1007/978-3-540-85451-7_97 | Euro-Par |
Keywords | Field | DocType |
critical path,chip,network on chip | End-to-end delay,Packet analyzer,Computer science,Transmission delay,Network scheduler,Computer network,Burst switching,Fast packet switching,Packet generator,Processing delay | Conference |
Volume | ISSN | Citations |
5168 | 0302-9743 | 27 |
PageRank | References | Authors |
1.12 | 11 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Crispín Gómez Requena | 1 | 160 | 12.57 |
| María Engracia Gómez | 2 | 149 | 17.48 |
| Pedro López | 3 | 233 | 16.39 |
| José Duato | 4 | 3481 | 294.85 |