Name
Abstract | ||
|---|---|---|
Power consumption of on-chip interconnects is a primary concern for many embedded system-on-chip (SoC) applications. In this paper, we compare energy and performance characteristics of asynchronous (clockless) and synchronous network-on-chip implementations, optimized for a number of SoC designs. We adapted the COSI-2.0 framework with ORION 2.0 router and wire models for synchronous network generation. Our own tool, ANetGen, specifies the asynchronous network by determining the topology with simulated-annealing and router locations with force-directed placement. It uses energy and delay models from our 65 nm bundled-data router design. SystemC simulations varied traffic burstiness using the self-similar b-model. Results show that the asynchronous network provided lower median and maximum message latency, especially under bursty traffic, and used far less router energy with a slight overhead for the inter-router wires. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/NOCS.2010.21 | Networks-on-Chip |
Keywords | Field | DocType |
synchronous network-on-chip implementation,asynchronous network,bursty traffic,router location,synchronous nocs,systemc simulation,bundled-data router design,delay model,router energy,synchronous network generation,soc design,topology,noc,soc,network,embedded system,design optimization,eda,asynchronous,routing protocols,cad,embedded systems,switches,network on chip,floorplan,chip,simulated annealing,a priori knowledge,system on a chip,network on a chip | Computer science,Computer network,Real-time computing,Asynchronous communication,System on a chip,Parallel computing,Network on a chip,SystemC,Burstiness,Router,Energy consumption,Routing protocol,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-4244-7086-0 | 11 | 0.58 |
References | Authors | |
29 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daniel Gebhardt | 1 | 11 | 0.58 |
| Junbok You | 2 | 47 | 3.79 |
| Kenneth S. Stevens | 3 | 185 | 25.65 |