Paper Info
Title
Effective Path Selection for Delay Fault Testing of Sequential Circuits
Abstract
This paper outlines several problems relatedto the delay fault testing of sequential circuits. For timingtest of a circuit and for layout optimization, critical pathdata are needed. When critical paths are identified by astatic timing analyzer, many of the selected paths cannotbe activated functionally. Such paths are sequential falsepaths. However, many of these paths can be activatedand tested in the full or partial scan mode due to theincreased controllability and observability. Therefore, itis possible that detection of a timing error on a sequentialfalse path, when scan mode is used, can lead to the rejectionof a functionally good circuit. We propose that thesepaths should not be targeted during delay test if scanmode is used. Similarly, sequential false paths should notbe used for layout optimization or for selection of maximumclock rate. We present a novel algorithm to identifythese paths. This algorithm is based on functional analysisof each target path for single and multiple path activation.If a path cannot be activated either way, it is sequentiallyfalse.
Year
DOI
Venue
1997
10.1109/TEST.1997.639716
ITC
Keywords
Field
DocType
activated functionally,sequential circuits,sequential circuit,multiple path activation,critical path,target path,layout optimization,sequential false path,delay fault testing,selected path,effective path selection,sequentialfalse path,sequential falsepaths,functional analysis,integrated circuit layout,observability,controllability,activation function,sequential analysis
Delay calculation,Integrated circuit layout,Observability,Sequential logic,Control theory,Computer science,Circuit extraction,Scan chain,Real-time computing,Electronic engineering,Static timing analysis,Critical path method
Conference
ISSN
ISBN
Citations 
1089-3539
0-7803-4209-7
11
PageRank 
References 
Authors
1.94
18
2
Name
Order
Citations
PageRank
Tapan J. Chakraborty125826.11
Vishwani D. Agrawal23502470.06