Name
Abstract | ||
|---|---|---|
Instruction Level Parallelism (ILP) extraction for multi-cluster VLIW processors is a very hard task. In this paper, we propose a retargetable architecture that can exploit ILP and thread level parallelism jointly, thus allowing an easier parallelism extraction and improving the performance with respect to traditional multicluster VLIW processors. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/DATE.2005.219 | DATE |
Keywords | Field | DocType |
retargetable architecture,traditional multicluster vliw processor,thread level parallelism,multicluster vliw processors,hard task,multi-cluster vliw processor,easier parallelism extraction,multithreaded extension,instruction level parallelism,multi threading,switches,parallel processing,dynamic scheduling,performance,vliw,computer architecture,embedded systems,registers | Instruction-level parallelism,Multithreading,Yarn,Computer science,Very long instruction word,Task parallelism,Parallel computing,Exploit,Real-time computing,Data parallelism,Dynamic priority scheduling | Conference |
ISSN | ISBN | Citations |
1530-1591 | 0-7695-2288-2 | 5 |
PageRank | References | Authors |
0.43 | 5 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Domenico Barretta | 1 | 6 | 1.12 |
| William Fornaciari | 2 | 543 | 67.45 |
| Mariagiovanna Sami | 3 | 314 | 39.98 |
| Daniele Bagni | 4 | 30 | 4.98 |