Name
Abstract | ||
|---|---|---|
Domino keeper has to be upsized to keep the noise margin in high fan-in dynamic gates, which increases the power consumption and slows down the evaluation. We propose a four-phase non-full swing keeper design to solve this dilemma. Non-full swing switching at the keeper gate together with alleviated contention help to reduce power consumption and delay. Simulation of 16-input OR gate using 0.13um CMOS SPICE parameters shows that proposed keeper design can reduce power consumption and delay by 26% and 24%, respectively. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ISQED.2004.1283710 | ISQED |
Keywords | Field | DocType |
noise margin,domino keeper,proposed keeper design,low power,high performance circuit techniques,high fan-in dynamic gates,high fan-in dynamic gate,four-phase non-full swing keeper,cmos spice parameter,power consumption,alleviated contention help,keeper gate,low power electronics,logic gates,vlsi,integrated circuit design,threshold voltage,very large scale integration,vlsi circuits | Logic gate,Computer science,Fan-in,CMOS,Electronic engineering,OR gate,Integrated circuit design,Noise margin,Electrical engineering,Energy consumption,Low-power electronics | Conference |
ISBN | Citations | PageRank |
0-7695-2093-6 | 9 | 0.86 |
References | Authors | |
5 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ge Yang | 1 | 20 | 2.16 |
| Zhongda Wang | 2 | 20 | 1.82 |
| Sung-Mo Steve Kang | 3 | 1198 | 213.14 |