Name
Abstract | ||
|---|---|---|
Before verifying the functionality of SoCs, designers must ensure the correctness of the pin-accurate interfaces of up to hundreds of integrated IP blocks. This article presents a new connection model and a corresponding error model for pin-accurate port connections, along with an algorithm for generating the minimum pattern set, a methodology for diagnosing errors, and a port connection verification flow. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/MDT.2008.149 | IEEE Design & Test of Computers |
Keywords | Field | DocType |
new connection model,pin-accurate interface,diagnosing error,port connection verification flow,pin-accurate port connection,minimum pattern set,integrated ip block,corresponding error model,pin-accurate port connections,testing,formal verification,diagnosis,soc,manganese,system on chip,verification | System on a chip,Pattern generation,Computer science,Correctness,Electronic engineering,Hardware design languages,Embedded system,Formal verification | Journal |
Volume | Issue | ISSN |
25 | 5 | 0740-7475 |
Citations | PageRank | References |
0 | 0.34 | 11 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Geeng-Wei Lee | 1 | 14 | 2.21 |
| Juinn-Dar Huang | 2 | 270 | 27.42 |
| Wang Chun-Yao | 3 | 251 | 36.08 |
| Jing-Yang Jou | 4 | 681 | 88.55 |