Paper Info
Title
Platform-Based Behavior-Level And System-Level Synthesis
Abstract
With the rapid increase of complexity in System-on-a-Chip (SoC) design, the electronic design automation (EDA) community is moving from RTL (Register 'IYansfer Level) synthesis to behavioral-level and system-level synthesis. The needs of system-level verification and software/hardware codesign also prefer behavior-level executable specifications, such as C or SystemC. In this paper we present the platform-based synthesis system, named xPilot, being developed at UCLA. The first objective of xPilot is to provide novel behavioral synthesis capability for automatically generating efficient RTL code from a C or SystemC description for a given system platform and optimizing the logic, interconnects, performance, and power simultaneously. The second objective of xPilot is to provide a platform-based system-level synthesis capability, including both synthesis for application-specific configurable processors and heterogeneous multi-core systems. Preliminary experiments on FPGAs demonstrate the efficacy of our approach on a wide range of applications and its value in exploring various design tradeoffs.
Year
DOI
Venue
2006
10.1109/SOCC.2006.283880
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS
Keywords
Field
DocType
fpga,logic design,system on chip,register transfer level,electronic design automation,field programmable gate arrays,high level synthesis,system on a chip
Logic synthesis,Computer architecture,System on a chip,Computer science,High-level synthesis,Field-programmable gate array,Real-time computing,SystemC,Electronic design automation,Register-transfer level,Executable,Embedded system
Conference
ISSN
Citations 
PageRank 
2164-1676
33
2.70
References 
Authors
6
5
Name
Order
Citations
PageRank
Jason Cong17069515.06
Yiping Fan245625.67
Guoling Han331317.17
Wei Jiang418211.40
Zhiru Zhang5102071.74