Name
Title | ||
|---|---|---|
Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation |
Abstract | ||
|---|---|---|
This paper proposes a theory of transistor short faults and their detection in logic test environment. We define transistor short models, and reveal the characteristics of equivalent faults and redundant faults. Also, we present a stuck-at fault simulation method and a test generation method that uses only the gate-level description of the circuits while dealing with transistor short faults. We present experimental results for ISCAS benchmark circuits to demonstrate the effectiveness of the methodology proposed in this paper. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/VLSID.2007.83 | VLSI Design |
Keywords | Field | DocType |
test generation method,fault coverage,fault efficiency,gate-level simulation,redundant fault,logic test environment,equivalent fault,transistor short fault,gate-level description,iscas benchmark circuit,stuck-at fault simulation method,test generation,transistor short model,automatic test pattern generation | Stuck-at fault,Automatic test pattern generation,Fault coverage,Computer science,Electronic engineering,Real-time computing,Logic simulation,Fault (power engineering),Electronic circuit,Transistor,Fault indicator | Conference |
ISSN | ISBN | Citations |
1063-9667 | 0-7695-2762-0 | 1 |
PageRank | References | Authors |
0.37 | 3 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoshinobu Higami | 1 | 140 | 27.24 |
| Kewal K. Saluja | 2 | 1483 | 141.49 |
| Hiroshi Takahashi | 3 | 148 | 24.32 |
| Yuzo Takamatsu | 4 | 150 | 27.40 |