Name
Affiliation
Papers
YOSHINOBU HIGAMI
Ehime University, Japan
64
Collaborators
Citations 
PageRank 
62
140
27.24
Referers 
Referees 
References 
218
731
506
Search Limit
100731
Title
Citations
PageRank
Year
Ff-Control Point Insertion (Ff-Cpi) To Overcome The Degradation Of Fault Detection Under Multi-Cycle Test For Post00.342020
Automotive Functional Safety Assurance by POST with Sequential Observation.10.382018
Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST00.342018
Evaluation of educational applications in terms of communication delay between tablets with Bluetooth or Wi-Fi Direct.00.342018
Trip-Based Integer Linear Programming Model For Static Multi-Car Elevator Operation Problems00.342017
On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects00.342017
A Method For Diagnosing Bridging Fault Between A Gate Signal Line And A Clock Line00.342017
Discrimination Of A Resistive Open Using Anomaly Detection Of Delay Variation Induced By Transitions On Adjacent Lines00.342017
Testing of Interconnect Defects in Memory Based Reconfigurable Logic Device (MRLD)20.392017
Harnessing Fuzziness of the Pragmatic Rule-Design Without IF-THEN Rules.00.342017
Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation20.412016
Evaluation of Influence Exerted by a Malicious Group's Various Aims in the External Grid.00.342016
Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays.00.342016
Design And Implementation Of Data Synchronization And Offline Capabilities In Native Mobile Apps00.342016
Giving formal roles to elevators for breaking symmetry in static elevator operation problems00.342015
Diagnosis of Delay Faults Considering Hazards00.342015
Sushi: A Lightweight Distributed Image Storage System for Mobile and Web Services00.342014
Optimal Periods for Probing Convergence of Infinite-stage Dynamic Programmings on GPUs.00.342014
Test Generation For Delay Faults On Clock Lines Under Launch-On-Capture Test Environment00.342013
Intermittently Proving Dynamic Programming to Solve Infinite MDPs on GPUs00.342013
Generation Of Diagnostic Tests For Transition Faults Using A Stuck-At Atpg Tool10.362012
Dynamic Routing and Wavelength Assignment with Backward Reservation in Wavelength-routed Multifiber WDM Networks.10.362012
Diagnosis for Bridging Faults on Clock Lines00.342012
Fault simulation and test generation for clock delay faults101.052011
On Detecting Transition Faults in the Presence of Clock Delay Faults20.382011
Test Pattern Selection for Defect-Aware Test00.342011
Enhancement of Clock Delay Faults Testing20.462011
Replica Selection and Downloading based on Wavelength Availability in λ-grid Networks.10.362010
Dynamic Parallel Downloading with Network Coding in $\lambda$-Grid Networks.10.352010
New Class of Tests for Open Faults with Considering Adjacent Lines20.382009
Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC50.502009
Addressing Defect Coverage Through Generating Test Vectors For Transistor Defects00.342009
A Novel Approach for Improving the Quality of Open Fault Diagnosis50.492009
An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation.00.342009
Diagnostic Test Generation For Transition Faults Using A Stuck-At Atpg Tool130.662009
Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools10.372008
Maximizing Stuck-Open Fault Coverage Using Stuck-At Test Vectors20.402008
Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information10.362008
Post-BIST Fault Diagnosis for Multiple Faults00.342008
Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults70.642008
Timing-Aware Diagnosis for Small Delay Defects40.452007
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines50.492007
Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation10.372007
Effective Post-BIST Fault Diagnosis for Multiple Faults10.392006
On Finding Don't Cares in Test Sequences for Sequential Circuits40.472006
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits90.742006
Test cost reduction for logic circuits: Reduction of test data volume and test application time30.452005
Failure analysis of open faults by using detecting/un-detecting information on tests30.432004
Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction10.352004
Generation Of Test Sequences With Low Power Dissipation For Sequential Circuits00.342004
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