Title
Impact of dual placement and routing on WDDL netlist security in FPGA
Abstract
The wave dynamic differential logic (WDDL) has been identified as a promising countermeasure to increase the robustness of cryptographic devices against differential power attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the routing in both the direct and complementary paths must be balanced. This paper tackles the problem of unbalance of dual-rail signals in WDDL design. We describe placement techniques suitable for tree-based and mesh-based FPGAs and quantify the gain they confer. Then, we introduce a timing-balance-driven routing algorithm which is architecture independent. Our placement and routing techniques proved to be very promising. In fact, they achieve a gain of 95%, 93%, and 85% in delay balance in treebased, simple mesh, and cluster-based mesh architectures, respectively. To reduce further the switch and delay unbalance in Mesh architecture, we propose a differential pair routing algorithm that is specific to cluster-basedmesh architecture. It achieves perfectly balanced routed signals in terms of wire length and switch number.
Year
DOI
Venue
2013
10.1155/2013/802436
Int. J. Reconfig. Comp.
Keywords
Field
DocType
timing-balance-driven routing algorithm,wddl design,differential power attack,differential pair,dual placement,delay unbalance,delay balance,wddl technique,mesh architecture,wave dynamic differential logic,wddl netlist security,cluster-based mesh architecture
Netlist,Architecture,Computer science,Cryptography,Parallel computing,Field-programmable gate array,Robustness (computer science),Real-time computing,Routing algorithm,Embedded system
Journal
Volume
Citations 
PageRank 
2013,
1
0.36
References 
Authors
25
3
Name
Order
Citations
PageRank
Emna Amouri1397.83
Habib Mehrez220039.21
Zied Marrakchi315228.68