Name
Abstract | ||
|---|---|---|
A new BIST TPG design that is comprised of an Adjacency-based TPG plus a conventional pseudo-random TPG (i.e. a LFSR) is presented in this paper. When used to generate test patterns for test-per-clock BIST, it reduces the number of transitions that occur in the CUT and hence decreases the average and peak power consumption during testing. Moreover, the total energy consumption during BIST is also reduced since the test length produced by the mixed TPG is roughly the same as the test length produced by a classical LFSR-based TPG to reach the same fault coverage. Note that this TPG design has been developed to deal with strongly connected circuits with a small number of inputs. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/ATS.2000.893667 | Asian Test Symposium |
Keywords | Field | DocType |
new bist tpg design,adjacency-based test pattern generator,test length,low power bist design,adjacency-based tpg,mixed tpg,small number,peak power consumption,test-per-clock bist,tpg design,test pattern,classical lfsr-based tpg,vlsi,system testing,very large scale integration,low power electronics,packaging,automatic test pattern generation,power generation,fault coverage | Adjacency list,Automatic test pattern generation,Fault coverage,Computer science,Real-time computing,Electronic engineering,Strongly connected component,Energy consumption,Very-large-scale integration,Built-in self-test,Low-power electronics | Conference |
ISBN | Citations | PageRank |
0-7695-0887-1 | 1 | 0.43 |
References | Authors | |
14 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| P. Girard | 1 | 478 | 41.91 |
| L. Guiller | 2 | 380 | 24.24 |
| C. Landrault | 3 | 1 | 0.43 |
| S. Pravossoudovitch | 4 | 689 | 54.12 |