Name
Title | ||
|---|---|---|
Small-Sized Leakage-Controlled Gated Sense Amplifier For 0.5-V Multi-Gigabit Dram Arrays |
Abstract | ||
|---|---|---|
A small-sized leakage-controlled gated sense amplifier (SA) and relevant circuits are proposed for 0.5-V multi-gigabit DRAM arrays. The proposed SA consists of a high-V-T PMOS amplifier and a low-V-T NMOS amplifier which is composed of high-V-T NMOSs and a low-V-T cross-coupled NMOS, and achieves 46% area reduction compared to a conventional SA with a low-V-T CMOS preamplifier. Separation of the proposed SA and a data-line pair achieves a sensing time of 6 ns and a writing time of 0.6 ns. Momentarily overdriving the PMOS amplifier achieves a restoring time of 13 ns. The gate level control of the high-V-T NMOSs and the gate level compensation circuit for PVT variations reduce the leakage current of the proposed SA to 2% of that without the control, and its effectiveness was confirmed using a 50-nm test chip. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1587/transele.E95.C.594 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
DRAM, low voltage, sense amplifier, mid-point sensing | Dram,Sense amplifier,Gigabit,Leakage (electronics),Direct-coupled amplifier,Electronic engineering,Low voltage,Engineering,Electrical engineering,Operational amplifier,Differential amplifier | Journal |
Volume | Issue | ISSN |
E95C | 4 | 1745-1353 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Akira Kotabe | 1 | 37 | 9.67 |
| Riichiro Takemura | 2 | 44 | 26.44 |
| Yoshimitsu Yanagawa | 3 | 16 | 2.95 |
| Tomonori Sekiguchi | 4 | 17 | 3.74 |
| Kiyoo Itoh | 5 | 78 | 23.29 |