Name
Abstract | ||
|---|---|---|
Cache memories constitute a large fraction of processor chip area and are highly vulnerable to soft errors caused by energetic particles. To protect these memories, most of the modern processors employ Error Detection Codes (EDCs) or Error Correction Codes (ECCs). EDCs/ECCs impose significant overheads in terms of area and energy; these overheads increase as a function of interleaving EDCs/ECCs to detect/correct multiple errors. This paper proposes a new cache architecture to minimize the area and energy overheads of EDCs/ECCs in set-associative L1-caches. Simulation results for a 4-way set-associative cache show that the proposed architecture reduces both the area and static power overheads of parity code by about 75% and the dynamic energy overhead by about 73% in comparison to conventional cache architecture. These reduction figures are about 68% and about 66%, respectively, for SEC-DED code. The above reductions are achieved without affecting the error coverage. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.7873/DATE.2014.177 | Design, Automation and Test in Europe Conference and Exhibition |
Keywords | Field | DocType |
dynamic energy overhead,low-cost fault-tolerant cache memory,cache memory,processor chip area,overheads increase,conventional cache architecture,energy overhead,4-way set-associative cache show,interleaving edcs,proposed architecture,new cache architecture,generators,error detection and correction,fault tolerance,reliability | Cache invalidation,Cache pollution,Computer science,Cache,Parallel computing,Cache-only memory architecture,Page cache,Cache algorithms,Real-time computing,Cache coloring,Smart Cache | Conference |
ISSN | Citations | PageRank |
1530-1591 | 2 | 0.36 |
References | Authors | |
3 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hamed Farbeh | 1 | 47 | 9.85 |
| Seyed Ghassem Miremadi | 2 | 531 | 50.32 |