Paper Info
Title
An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology
Abstract
The de facto modeling method to analyze channel-hot-carrier (CHC) is based on substrate current (Isub), which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this work, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions, for both negative-bias-temperature-instability (NBTI) and CHC degradation. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65 nm technology. We benchmark the prediction of circuit performance degradation with measured ring oscillator data and simulations of an amplifier.
Year
DOI
Venue
2007
10.1109/CICC.2007.4405783
CICC
Keywords
Field
DocType
circuit reliability,cmos integrated circuits,integrated circuit reliability,chc degradation,integrated circuit modelling,surface potential,size 65 nm,transistor parameters,hot carriers,channel-hot-carrier,cmos technology,negative-bias-temperature-instability,ring oscillator data,general reaction-diffusion model,substrate current,integrated modeling paradigm,leakage components,de facto modeling method,ring oscillator,reaction diffusion,negative bias temperature instability
Discrete circuit,Ring oscillator,Computer science,Circuit reliability,Circuit design,Electronic engineering,Control engineering,CMOS,Subthreshold conduction,Transistor,Integrated circuit,Electrical engineering
Conference
ISBN
Citations 
PageRank 
978-1-4244-1623-3
12
0.89
References 
Authors
3
6
Name
Order
Citations
PageRank
Wenping Wang11376.74
Vijay Reddy2120.89
Anand T. Krishnan39451.97
Rakesh Vattikonda433827.20
Srikanth Krishnan515957.15
Yu Cao632929.78