Name
Abstract | ||
|---|---|---|
Microprocessor design is a very complex and time-consuming activity. One of the primary reasons is the huge design space that needs to be explored in order to identify the optimal design given a number of constraints. Simulations are usually used to explore these huge design spaces, however, they are fairly slow. Several hundreds of billions of instructions need to be simulated per benchmark; and this needs to be done for every design point of interest.Recently, statistical simulation was proposed to efficiently cull a huge design space. The basic idea of statistical simulation is to collect a number of important program characteristics and to generate a synthetic trace from it. Simulating this synthetic trace is extremely fast as it contains a million instructions only.This paper improves the statistical simulation methodology by proposing accurate memory data flow models. We model (i) load forwarding, (ii) delayed cache hits, and (iii) correlation between cache misses based on path info. Our experiments using the SPEC CPU2000 benchmarks show a substantial improvement upon current state-of-the-art statistical simulation methods. For example, for our baseline configuration we reduce the average IPC prediction error from 10.7% to 2.3%. In addition, we show that performance trends are predicted very accurately, making statistical simulation enhanced with accurate data flow models a useful tool for efficient and accurate microprocessor design space explorations. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1145/1183401.1183415 | I4CS |
Keywords | Field | DocType |
design point,accurate memory data,microprocessor design,accurate microprocessor design space,optimal design,huge design space,synthetic trace,accurate data flow model,statistical simulation,current state-of-the-art statistical simulation,statistical simulation methodology,data flow,prediction error,point of interest | Design space,Statistical simulation,Cache,Computer science,Parallel computing,Baseline (configuration management),Real-time computing,Optimal design,Space exploration,Spec#,Data flow diagram | Conference |
ISBN | Citations | PageRank |
1-59593-282-8 | 8 | 0.64 |
References | Authors | |
20 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Davy Genbrugge | 1 | 60 | 2.82 |
| Lieven Eeckhout | 2 | 2863 | 195.11 |
| Koen De Bosschere | 3 | 1659 | 117.74 |