Name
Title | ||
|---|---|---|
Maximum Power Supply Noise Estimation In Vlsi Circuits Using Multimodal Genetic Algorithms |
Abstract | ||
|---|---|---|
This paper presents a genetic algorithm (GA) based method for finding the maximum voltage drop in the power bus of digital VLSI circuits. The worst-case voltage drop at a specified node in the power bus is defined as the fitness value for different input-vector pairs. A gate-level simulator and a sparse linear solver are applied to compute the fitness value. A sharing technique is applied to find the global optima accurately and rapidly. Comparisons with input-independent simulations for Circuits extracted from layouts arc used to validate our approach. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/ICECS.2001.957485 | ICECS |
Keywords | DocType | Volume |
genetic algorithm,threshold voltage,computational modeling,power systems,space technology,genetic algorithms,power bus,very large scale integration,vlsi | Conference | 3 |
Citations | PageRank | References |
2 | 0.55 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| G. Bai | 1 | 9 | 1.17 |
| S. Bobba | 2 | 110 | 16.06 |
| I. Haji | 3 | 2 | 0.55 |
| Ibrahim N. Hajj | 4 | 572 | 79.52 |