Name
Abstract | ||
|---|---|---|
Complex embedded systems are typically specified using multiple domain-specific languages. After code-generation, the implementation is simulated and tested. Validation of non-functional properties, in particular timing, remains a problem because full test coverage cannot be achieved for realistic designs. The alternative, formal timing analysis, requires a system representation based on key application and architecture properties. These properties must first be extracted from a system specification to enable analysis. In this paper we present a suitable transformation of SDL specifications for system-level timing analysis. We show ways to vary modeling accuracy in order to apply available formal techniques. A practical approach utilizing a recently developed system model is presented. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1145/774789.774815 | Estes Park, CO |
Keywords | Field | DocType |
available formal technique,system-level timing analysis,architecture property,system specification,system model,formal timing analysis,complex embedded system,system representation,sdl specification,particular timing,test coverage,computational modeling,timing analysis,domain specific languages,code generation,testing,systems analysis,formal specification,system level design,embedded systems,domain specific language,system modeling,finite state machines,real time systems,computer architecture,embedded system | Domain-specific language,Code coverage,Programming language,Computer science,Systems analysis,Electronic system-level design and verification,Formal specification,Static timing analysis,System requirements specification,System model | Conference |
ISBN | Citations | PageRank |
1-58113-542-4 | 3 | 0.60 |
References | Authors | |
12 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Marek Jersak | 1 | 305 | 25.27 |
| Kai Richter | 2 | 384 | 34.65 |
| Rafik Henia | 3 | 161 | 13.71 |
| Rolf Ernst | 4 | 2633 | 252.90 |
| Frank Slomka | 5 | 3 | 0.60 |